The invention relates generally to memory devices, and more specifically, to a memory device having a plurality of banks, each bank comprising a plurality of memory cells. The invention relates further to a related design structure.
Wide memory arrays of SRAM cells with long word lines in upcoming 14 nm semiconductor production technologies typically use a write assist circuit to ensure cell write-ability. This technology uses a single reduced voltage for the array. Additionally, the cells may be pretty stable due to the transistor characteristics (fully depleted FIN-FETs). The tuning options may be limited. Furthermore it is not possible to build half FINs, i.e., the gate-width may only be varied in discrete steps and doping is more and difficult to control. This may cause that safe write operations for memory cells may be critical. Therefore, the bit-lines use a negative voltage pulse to assist and thus, improve/ensure cell write-ability.
The electrical behavior of a bit-line is dominated by its capacitance. To drive the bit-line below ground, a boost capacitor may be required. The state-of-the-art NBA (negative bias write assist) circuitry requires a boost capacitor, that has to scale with the total bit-line capacitance and therefore with the number of data words a memory can store. For large arrays, the state-of-the-art NBA consumes a significant amount of area and power.